1. Field of the Invention
This invention relates in general to integrated circuits.
2. Description of the Related Art
Some integrated circuits utilize N-channel transistors and P-channel transistors having spacer insulating regions adjacent to the gates of these transistors. Typically, the spacer insulating regions are the same width for both the N-channel transistors and the P-channel transistors.
The stress of the lattice of a transistor channel may affect performance of a P-channel transistor differently than that of an N-channel transistor. Typically, increased compressive stress (or reduced tensile stress) on a channel lattice will improve the performance (e.g. improved drive current) of a P-channel transistor but decrease the performance of an N-channel transistor.
What is needed is an integrated circuit with improved performance for both N-channel and P-channel transistors.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The structures shown in the Figures are not necessarily drawn to scale.